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Hans Schou <sslug@sslug> writes:
> Har du x86info installeret?
Nej, jeg kunne ikke huske hvad det hed. Hvis I prøver dette her, så
skal I huske at computeren skal slukkes helt, hvis I vil slå
serialnumber til efter det har været slået fra. reboot(8) var ikke nok
for mig.
Hermed kommer x86info. Først fra hvor det er slået fra:
plugh% ./x86info
x86info v1.3. Dave Jones 2001
Feedback to <sslug@sslug>.
Found 1 CPU
Intel-specific functions
Family: 6 Model: 8 Type 0 [Celeron / Pentium III (Coppermine) Original OEM]
Stepping: 6
Reserved: 0
plugh% ./x86info -a
x86info v1.3. Dave Jones 2001
Feedback to <sslug@sslug>.
Found 1 CPU
eax in: 0, eax = 00000002 ebx = 756e6547 ecx = 6c65746e edx = 49656e69
eax in: 1, eax = 00000686 ebx = 00000002 ecx = 00000000 edx = 0383f9ff
eax in: 2, eax = 03020101 ebx = 00000000 ecx = 00000000 edx = 0c040882
Vendor ID: "GenuineIntel"; Max CPUID level 2
Intel-specific functions
Family: 6 Model: 8 Type 0 [Celeron / Pentium III (Coppermine) Original OEM]
Stepping: 6
Reserved: 0
Feature flags 0383f9ff:
FPU Floating Point Unit
VME Virtual 8086 Mode Enhancements
DE Debugging Extensions
PSE Page Size Extensions
TSC Time Stamp Counter
MSR Model Specific Registers
PAE Physical Address Extension
MCE Machine Check Exception
CX8 COMPXCHG8B Instruction
SEP Fast System Call
MTRR Memory Type Range Registers
PGE PTE Global Flag
MCA Machine Check Architecture
CMOV Conditional Move and Compare Instructions
FGPAT Page Attribute Table
PSE-36 36-bit Page Size Extension
MMX MMX instruction set
FXSR Fast FP/MMX Streaming SIMD Extensions save/restore
XMM Streaming SIMD Extensions instruction set
Instruction TLB: 4KB pages, 4-way set assoc, 32 entries
Instruction TLB: 4MB pages, fully assoc, 2 entries
Data TLB: 4KB pages, 4-way set assoc, 64 entries
L2 unified cache: Sectored, 32 byte cache line, 8 way set associative, 256K
Instruction cache: 16KB, 4-way set assoc, 32 byte line size
Data TLB: 4MB pages, 4-way set assoc, 8 entries
Data cache: 16KB, 2-way or 4-way set assoc, 32 byte line size
Need to be root to access MSRs.
2MHz processor (estimate).
plugh%
Dernæst med serialnumber slået til:
plugh% ./x86info
x86info v1.3. Dave Jones 2001
Feedback to <sslug@sslug>.
Found 1 CPU
Intel-specific functions
Family: 6 Model: 8 Type 0 [Celeron / Pentium III (Coppermine) Original OEM]
Stepping: 6
Reserved: 0
Processor serial: 0000-0686-0003-5D6F-CA00-A9D9
plugh% ./x86info -a
x86info v1.3. Dave Jones 2001
Feedback to <sslug@sslug>.
Found 1 CPU
eax in: 0, eax = 00000003 ebx = 756e6547 ecx = 6c65746e edx = 49656e69
eax in: 1, eax = 00000686 ebx = 00000002 ecx = 00000000 edx = 0387f9ff
eax in: 2, eax = 03020101 ebx = 00000000 ecx = 00000000 edx = 0c040882
eax in: 3, eax = 00000000 ebx = 00000000 ecx = ca00a9d9 edx = 00035d6f
Vendor ID: "GenuineIntel"; Max CPUID level 3
Intel-specific functions
Family: 6 Model: 8 Type 0 [Celeron / Pentium III (Coppermine) Original OEM]
Stepping: 6
Reserved: 0
Feature flags 0387f9ff:
FPU Floating Point Unit
VME Virtual 8086 Mode Enhancements
DE Debugging Extensions
PSE Page Size Extensions
TSC Time Stamp Counter
MSR Model Specific Registers
PAE Physical Address Extension
MCE Machine Check Exception
CX8 COMPXCHG8B Instruction
SEP Fast System Call
MTRR Memory Type Range Registers
PGE PTE Global Flag
MCA Machine Check Architecture
CMOV Conditional Move and Compare Instructions
FGPAT Page Attribute Table
PSE-36 36-bit Page Size Extension
PN Processor Serial Number present and enabled
MMX MMX instruction set
FXSR Fast FP/MMX Streaming SIMD Extensions save/restore
XMM Streaming SIMD Extensions instruction set
Instruction TLB: 4KB pages, 4-way set assoc, 32 entries
Instruction TLB: 4MB pages, fully assoc, 2 entries
Data TLB: 4KB pages, 4-way set assoc, 64 entries
L2 unified cache: Sectored, 32 byte cache line, 8 way set associative, 256K
Instruction cache: 16KB, 4-way set assoc, 32 byte line size
Data TLB: 4MB pages, 4-way set assoc, 8 entries
Data cache: 16KB, 2-way or 4-way set assoc, 32 byte line size
Processor serial: 0000-0686-0003-5D6F-CA00-A9D9
Need to be root to access MSRs.
1MHz processor (estimate).
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Last modified
2005-08-10, 19:23 CEST
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